Oscillator Diagramについて。
ConfigSet クロック関係はこの図を見ながら設定していく。
関係も至ってシンプル。のように見える。
使い込んでいくとわからない部分も出てくるのかもしれないが・・・
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| Oscillator Diagram |
| // PLL Input Divider: | |
| #pragma config FPLLIDIV = DIV_1 | // 1x Divider |
| #pragma config FPLLIDIV = DIV_2 | // 2x Divider |
| #pragma config FPLLIDIV = DIV_3 | // 3x Divider |
| #pragma config FPLLIDIV = DIV_4 | // 4x Divider |
| #pragma config FPLLIDIV = DIV_5 | // 5x Divider |
| #pragma config FPLLIDIV = DIV_6 | // 6x Divider |
| #pragma config FPLLIDIV = DIV_10 | // 10x Divider |
| #pragma config FPLLIDIV = DIV_12 | // 12x Divider |
| // PLL Multiplier: | |
| #pragma config FPLLMUL = MUL_15 | // 15x Multiplier |
| #pragma config FPLLMUL = MUL_16 | // 16x Multiplier |
| #pragma config FPLLMUL = MUL_17 | // 17x Multiplier |
| #pragma config FPLLMUL = MUL_18 | // 18x Multiplier |
| #pragma config FPLLMUL = MUL_19 | // 19x Multiplier |
| #pragma config FPLLMUL = MUL_20 | // 20x Multiplier |
| #pragma config FPLLMUL = MUL_21 | // 21x Multiplier |
| #pragma config FPLLMUL = MUL_24 | // 24x Multiplier |
| // USB PLL Input Divider: | |
| #pragma config UPLLIDIV = DIV_1 | // 1x Divider |
| #pragma config UPLLIDIV = DIV_2 | // 2x Divider |
| #pragma config UPLLIDIV = DIV_3 | // 3x Divider |
| #pragma config UPLLIDIV = DIV_4 | // 4x Divider |
| #pragma config UPLLIDIV = DIV_5 | // 5x Divider |
| #pragma config UPLLIDIV = DIV_6 | // 6x Divider |
| #pragma config UPLLIDIV = DIV_10 | // 10x Divider |
| #pragma config UPLLIDIV = DIV_12 | // 12x Divider |
| // USB PLL Enable: | |
| #pragma config UPLLEN = ON | // Enabled |
| #pragma config UPLLEN = OFF | // Disabled and Bypassed |
| // System PLL Output Clock Divider: | |
| #pragma config FPLLODIV = DIV_1 | // PLL Divide by 1 |
| #pragma config FPLLODIV = DIV_2 | // PLL Divide by 2 |
| #pragma config FPLLODIV = DIV_4 | // PLL Divide by 4 |
| #pragma config FPLLODIV = DIV_8 | // PLL Divide by 8 |
| #pragma config FPLLODIV = DIV_16 | // PLL Divide by 16 |
| #pragma config FPLLODIV = DIV_32 | // PLL Divide by 32 |
| #pragma config FPLLODIV = DIV_64 | // PLL Divide by 64 |
| #pragma config FPLLODIV = DIV_256 | // PLL Divide by 256 |
| // Oscillator Selection Bits: | |
| #pragma config FNOSC = FRC | // Fast RC Osc (FRC) |
| #pragma config FNOSC = FRCPLL | // Fast RC Osc with PLL |
| #pragma config FNOSC = PRI | // Primary Osc (XT,HS,EC) |
| #pragma config FNOSC = PRIPLL | // Primary Osc w/PLL (XT+,HS+,EC+PLL) |
| #pragma config FNOSC = SOSC | // Low Power Secondary Osc (SOSC) |
| #pragma config FNOSC = LPRC | // Low Power RC Osc (LPRC) |
| #pragma config FNOSC = FRCDIV16 | // Fast RC Osc w/Div-by-16 (FRC/16) |
| #pragma config FNOSC = FRCDIV | // Fast RC Osc w/Div-by-N (FRCDIV) |
| // Secondary Oscillator Enable: | |
| #pragma config FSOSCEN = OFF | // Disabled |
| #pragma config FSOSCEN = ON | // Enabled |
| // Internal/External Switch Over: | |
| #pragma config IESO = OFF | // Disabled |
| #pragma config IESO = ON | // Enabled |
| // Primary Oscillator Configuration: | |
| #pragma config POSCMOD = EC | // External clock mode |
| #pragma config POSCMOD = XT | // XT osc mode |
| #pragma config POSCMOD = HS | // HS osc mode |
| #pragma config POSCMOD = OFF | // Primary osc disabled |
| // CLKO Output Signal Active on the | // OSCO Pin: |
| #pragma config OSCIOFNC = ON | // Enabled |
| #pragma config OSCIOFNC = OFF | // Disabled |
| // Peripheral Clock Divisor: | |
| #pragma config FPBDIV = DIV_1 | // Pb_Clk is Sys_Clk/1 |
| #pragma config FPBDIV = DIV_2 | // Pb_Clk is Sys_Clk/2 |
| #pragma config FPBDIV = DIV_4 | // Pb_Clk is Sys_Clk/4 |
| #pragma config FPBDIV = DIV_8 | // Pb_Clk is Sys_Clk/8 |
| // Clock Switching and Monitor Selection: | |
| #pragma config FCKSM = CSECME | // Clock Switch Enable, FSCM Enabled |
| #pragma config FCKSM = CSECMD | // Clock Switch Enable, FSCM Disabled |
| #pragma config FCKSM = CSDCMD | // Clock Switch Disable, FSCM Disabled |
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